1. Field of the Invention
The present invention relates generally to synchronous random access memories (hereinafter referred to as synchronous RAMs), and more specifically, to a high speed synchronous RAM used for improving the speed performance of a computer.
2. Description of the Background Art
A synchronous RAM is a memory which operates in synchronization with an externally applied signal. A typical example of such a synchronous RAM is a synchronous static random access memory (hereinafter referred to as synchronous SRAM).
Synchronous SRAMs are used for cache memories provided for improving speed performance in computers of various levels such as supercomputer, large size calculator, work station, and personal computer.
Conventional synchronous SRAMs as such are disclosed in Japanese Patent Laying-Open No. 2-137189, Japanese Patent Publication No. 1-58591, and Japanese Patent Laying-Open No. 62-250583.
Japanese Patent Laying-Open No. 2-137189 discloses that a plurality of circuits in a memory are formed into a latch and controlled with a clock, in order to reduce cycle time. Japanese Patent Publication No. 1-58591 discloses that an input latch circuit for address signals and a circuit for latching outputs from a decode circuit are operated in a complementary manner with a single clock signal. Japanese Patent Laying-Open No. 62-250583 discloses producing of an internal write enable signal in response to an externally applied clock signal.
Now, a conventional general synchronous SRAM will be described. FIG. 9 is a block diagram showing an example of a conventional synchronous SRAM.
Referring to FIG. 9, the synchronous SRAM includes a memory core 50, latch circuits 11, 12, 16xcx9c19, 25, and 26, buffer circuits 63, 67, and 68, inverter circuits 64 and 69, and a tri-state buffer circuit 68.
Memory core 50 includes a memory cell array 51, a decoder 52, a read circuit 53 and a write circuit 54. Decoder 52, read circuit 53, and write circuit 54 are connected to memory cell array 51.
An externally applied address signal ADD is input from an address input pin 1, and applied to decoder 52 as an internal address signal RADD through buffer circuit 61, and latch circuits 11 and 16. An externally applied write enable signal NWE input from a control input pin 2 is applied to read circuit 53 and write circuit 54 as an internal write enable signal NWEin through buffer circuit 62, and latch circuits 12 and 17.
Read data RD output from read circuit 53 is applied to a data input/output pin 4 through latch circuits 18, 19 and tri-state buffer circuit 68 and externally output therefrom. Thus, tri-state buffer 68 acts as an output buffer circuit. Externally applied write data is input from input/output pin 4 and is applied to write circuit 54 as write data WD through buffer circuit 67, and latch circuits 26 and 25.
An externally applied clock signal K is input from a clock input pin 5. Buffer circuit 63 outputs an internal clock signal PH1 in response to external clock signal K. Inverter 64 outputs an internal clock signal PH2 which is the inverse of internal clock signal PH1 in response to external clock signal K.
Latch circuits 16, 17, 19 and 25 operate in response to internal clock signal PH1. Latch circuits 11, 12, 18, and 26 operate in response to internal clock signal PH2. These latch circuits each propagate input data to each output if an applied internal clock signal is in H level, and latch data for output if the applied internal clock signal is in L level.
In FIG. 9, the latch circuits which receive internal clock signal PH1 are denoted by xe2x80x9cPH1xe2x80x9d, and the latch circuits which receive internal clock signal PH2 are denoted at xe2x80x9cPH2xe2x80x9d for ease of illustration.
An external output enable signal NOE input from a control input pin 3 is inverted at inverter 69 and applied to tri-state buffer circuit 68 as a control signal. The three states of tri-state buffer circuit 68 are controlled in response to the control signal. More specifically, tri-state buffer 68 is activated if external enable signal NOE is in L level, and attains a high impedance state if external output enable signal NOE is in H level.
Other conventional synchronous SRAMs will be described. FIG. 10 is a block diagram showing the structure of another conventional synchronous SRAM.
Referring to FIG. 10, unlike the synchronous SRAM shown in FIG. 9, the synchronous SRAM is not provided with latch circuit 26 as shown in FIG. 9. Therefore, the synchronous SRAM shown in FIG. 10 which operates basically the same as the synchronous SRAM in FIG. 9 has a slightly different timing specification for the absence of latch circuit 26.
The synchronous SRAMs shown in FIGS. 9 and 10 each do not have any latch circuit which operates in response to internal clock signal PH1 or PH2 in the path until input of external output enable signal NOE into tri-state buffer circuit 68. Tri-state buffer circuit 68 operates asynchronously with respect to external clock signal K.
Besides, a latch circuit may be provided in the path until input of external output enable signal NOE into tri-state buffer 68. Such a synchronous SRAM has a slightly different timing specification from the synchronous SRAMs in FIGS. 9 and 10.
Operations of the conventional synchronous SRAMs shown in FIGS. 9 and 10 will be described. As described above, the synchronous SRAMs shown in FIGS. 9 and 10 operate basically in the same manner, and therefore the synchronous SRAM shown in FIG. 10 will be described by way of illustration.
FIG. 11 is a timing chart for use in illustration of the synchronous SRAM shown in FIG. 10. Illustrated in FIG. 11 are external clock signal K, external write enable signal NWE, external address signal ADD, data input/output signal DQ and external output enable signal NOE.
Herein, the period in which external clock signal K attains H level is called first phase Ph1, and the period in which external clock signal K attains L level is called second phase Ph2. First phase Ph1 corresponds to the period in which internal clock signal PH1 attains H level, and second phase Ph2 corresponds to the period in which internal clock signal PH2 attains H level.
First phase Ph1 and second phase Ph2 as such constitute one cycle for operation of the synchronous SRAM.
In FIG. 11, a first cycle CY1 to a seventh cycle CY7 are shown. In the series of cycles, writing, reading, writing, reading and reading operations are sequentially executed. The writing operations herein include not only writing of data into memory cell array 51 but also operations related to input of external address signal ADD and write data for the data writing.
The reading operations herein include not only data reading from memory cell array 51 but also operations related to input of an external address signal for the data reading and external output of the read data.
For the above writing operations, cycles for writing of data into memory cell array 51 are denoted by xe2x80x9cWRITExe2x80x9d in the figure, and for the above reading operations, cycles for data reading from memory cell array 51 are denoted by xe2x80x9cREADxe2x80x9d. Data input/output to/from data input/output pin 4 is illustrated at DQ.
In operation, it is assumed that external address signal ADD passes through latch circuit 11 and external write enable signal NWE passes through latch circuit 12 in the second phase of a cycle immediately before first cycle CY1.
Then in the first phase Ph1 of first cycle CY1, internal clock signal PH2 attains L level. Thus, external address signal ADD and external write enable signal NWE are latched by latch circuits 11 and 12, respectively.
In first phase Ph1, internal clock signal PH1 attains H level. Thus, the latched external address signal ADD is applied to decoder 52 as internal address signal RADD through latch circuit 16. At the time, the latched external write enable signal NWE is applied as internal write enable signal NWEin to read circuits 53 and write circuit 54 through latch circuit 17.
Meanwhile, in first cycle CY1, write data Din0 is input at data input/output pin 4 and applied to latch circuit 25 through buffer circuit 67. At the time, output enable signal NOE is in H level, and in response, tri-state buffer circuit 68 is in a high impedance state. Write data Din0 is thus input.
In first cycle CY1, latch circuit 25 passes write data Din0 in first phase Ph1, and latches write data Din0 in second phase Ph2. Thus, in first cycle CY1, write data Din0 is applied from data input/output pin 4 to write circuit 54 via buffer circuit 67 and latch circuit 25.
Therefore, in the period of first cycle CY1, data is written into a memory cell in memory cell array 51 which is selected based on internal address signal RADD applied to decoder 52.
Then, reading of data is executed. In the first phase Ph1 of second cycle CY2, internal address signal RADD indicating address A1 is applied to decoder 52, and internal write enable signal NWEin in H level is applied to read circuit 53 and write circuit 54.
Since internal write enable signal NWEin is in H level, read circuit 53 operates. Thus, data is read out from a memory cell in memory cell array 51 which is selected based on address A1.
In the second phase Ph2 of second cycle CY2, latch circuit 18 passes data RD read out from read circuit 53 (hereinafter referred to as read data). Then, in the first phase Ph1 of third circle CY3, latch circuit 19 passes read data RD applied from latch circuit 18.
Since in this state, external output enable signal NOE is in L level, tri-state buffer circuit 68 externally outputs the read data passed through latch circuit 19 from data input/output pin 4. The read data is denoted by xe2x80x9cDout1xe2x80x9d in FIG. 11.
Thus, in a conventional synchronous SRAM, a writing operation is executed in one cycle while a reading operation is executed in two cycles.
The above conventional synchronous SRAM is however encountered with the following disadvantage. If, for example, reading operations and writing operations are executed in a sequence as illustrated in FIG. 11, and a reading operation is executed following a writing operation, read data Dout1 read in second cycle CY2 is being output at data input/output pin 4 as shown in third cycle CY3. Accordingly, in third cycle CY3, write data cannot be taken in from data input/output pin 4, and therefore data cannot be written. The data writing operation therefore must be executed in fourth cycle CY4, one cycle delayed from third cycle CY3.
Data cannot be written in third cycle CY3 as described above directly because read data and write data collide with each other. Such state is generally called resource conflict.
Such conflict of resources will be more specifically described. A synchronous SRAM is roughly divided into three resources. The first resource is memory core 50. The second resource is the address/control input bus, in other words address input pin 1 and control input pins 2 and 3. The third resource is the data bus, in other words data input/output pin 4.
FIG. 12 is a schematic representation for use in illustration of timings for basic use of the resources of a conventional synchronous SRAM. In FIG. 12, a timing for use of the resources at the time of reading operation and a timing for use of resources at the time of writing operation are shown.
In FIG. 12, the first resource is represented as RAM. The second resource is represented as AD. The third resource is represented as DIN and DOUT. Resource DIN corresponds to input/output pin 4 used at input of write data, and resource DOUT corresponds to data input/output pin 4 used at output of read data.
In FIG. 12, the longitudinal side of the block of each resource corresponds to time. A reading operation is indicated as xe2x80x9cREADxe2x80x9d and a writing operation is indicated as xe2x80x9cWRITExe2x80x9d.
Three use cycles #1 to #3 are necessary for executing a reading operation. More specifically, in first use cycle #1, resource AD is used in response to input of external address signal ADD, and in the second use cycle #2 resource RAM is used for data reading from memory cell array 51, and in the third use cycle #3 resource DOUT is used for externally outputting the read data.
Meanwhile, two use cycles #1 and #2 are necessary for executing a writing operation. More specifically, in first use cycle #1, resource AD is used in response to input of address signal ADD, and in the second use cycle #2 resource DIN and resource RAM are used for input of data and writing of the data.
Now, an operation of a conventional synchronous SRAM in a timing for use of the resources as shown in FIG. 12 will be described.
FIG. 13 is a schematic representation showing timings for use of resources at the operation of a conventional synchronous SRAM. In FIG. 13, timings for use of resources are shown when writing, reading, reading, writing, writing, reading and writing operations are sequentially executed. The longitudinal direction also corresponds to time in FIG. 13.
Referring to FIG. 13, a series of writing and reading operations should be executed basically as follows for implementation of high speed operation of the synchronous SRAM. More specifically, immediately after use of resource AD for a writing operation or a reading operation is completed, that resource AD is used for the next writing or reading operation.
Operations conducted on such basis however cause a conflict of resources, because resource DOUT and resource DIN are used in the same use cycle in a writing operation executed immediately after a reading operation. Accordingly, in the series of operations in FIG. 13, a writing operation immediately after a reading operation is delayed (STL in FIG. 13) in order to avoid such a conflict of resources.
Such delay of writing operation however impedes the high speed operation of the synchronous SRAM.
As a solution to this problem, data input/output pin 4 could be divided into an input dedicated pin and an output dedicated pin. In this case, however, the number of pins increases which pushes up chip cost and package cost, and in addition the area of the board for packaging increases, resulting in increase of system cost.
It is an object of the invention to provide a synchronous random access memory permitting high speed operation of cache memories and improvement of the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers.
Another object of the invention is to provide a synchronous random access memory which eliminates delay of a writing operation immediately after a reading operation without increasing chip cost, package cost, and system cost.
Yet another object of the invention is to prevent a conflict of resources in a synchronous random access memory.
A synchronous random access memory according to the present invention includes a memory cell array, a read/write circuit, a data hold circuit, an address signal hold circuit, a select circuit, a decode circuit, a comparison circuit and a select output circuit.
The memory cell array includes a plurality of memory cells. The read/write circuit responds to a read/write control signal and reads/writes from/to a memory cell in the memory cell array selected corresponding to an internal address signal based on an external address signal.
The data hold circuit takes in data for writing into a memory cell in the memory cell array and holds the data excluding the period during which data is being externally output. The address signal hold circuit holds an internal address signal corresponding to the data held by the data hold circuit.
The select circuit receives an internal address signal for reading data, and the internal address signal held in the address signal hold circuit, and selectively outputs these internal address signals in response to a read/write control signal for reading or writing.
The decode circuit selects a memory cell in the memory cell array in response to the internal address signal output from the select circuit. The comparison circuit compares the internal address signal for reading data and the internal address signal held by the address hold circuit in order to output data.
The select output circuit receives the data held by the data hold circuit and the data read out by the read/write circuit, and selectively outputs these data based on the result of comparison by the comparison circuit, when data is externally read out.
The data to be written into the memory cell array is taken and held by the data hold circuit in a timing in which data is not being externally output. Accordingly, a conflict of resources does not occur between read data and write data.
The internal address signal corresponding to the data held in the data hold circuit is held by the address hold circuit and the held internal address signal is applied to the decode circuit from the select circuit at the time of writing in response to the read/write control signal.
Accordingly, the period to use the memory cell array for writing of the held data can be prolonged through the following period in which the memory cell array is not used at the time of data writing.
Therefore, a conflict of resources does not occur in the memory cell array. In addition, if held data is read out, the held internal address signal coincides with the internal address for reading data.
Therefore, if such a coincidence is found based on a comparison result from the comparison circuit, the held data may be output from the select output circuit. Accordingly, a request of reading data which has not yet been written in the memory cell array can be coped with.
Since a conflict of resources can be prevented as described above, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost. As a result, high speed operation of cache memories can be achieved, and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be achieved.
In addition, an internal clock generation circuit, a first logic circuit, and a second logic circuit may be further provided, and the data hold circuit may include a first latch circuit and the address signal hold circuit may include a second latch circuit.
In such a case, the internal clock generation circuit generates an internal clock signal in response to an external clock signal. The first logic circuit generates a first logic signal in response to a delayed read/write control signal and the internal clock signal. The first latch circuit latches data to be written in a memory cell in the memory cell array in response to the first logic signal. The second logic circuit generates a second logic signal in response to the internal clock signal and the read/write control signal. The second latch circuit latches an internal address signal corresponding to data held by the data hold circuit in response to the internal clock signal and the read/write control signal.
In addition, the select circuit may include a first multiplexer circuit, and the select output circuit may include a second multiplexer circuit.
The first multiplexer circuit applies an internal address signal for reading data to the decode circuit when the read/write control signal designates a reading, and applies an internal address signal held by the address hold circuit to the decode circuit when the read/write control signal designates a writing.
The second multiplexer circuit outputs data held by the data hold circuit when the internal address signals compared by the comparison circuit coincide, and outputs data read out by the read/write circuit when the internal address signals compared by the comparison circuit do not coincide.
A synchronous random access memory according to another aspect of the invention includes a memory cell array, a read/write circuit, a data hold circuit, an address signal hold circuit, a first select circuit, a decode circuit, a comparison circuit, a second select circuit and a select output circuit.
The memory cell array includes a plurality of memory cells. The read/write circuit responds to a read/write control signal and reads/writes data from/to a memory cell in the memory cell array selected corresponding to an internal address signal based on an external address signal.
The data hold circuit sequentially takes in a plurality of pieces of data for writing into memory cells in the memory cell array and holds the data in a sequence excluding the period during which the data is being externally output. The address signal hold circuit holds internal clock signals corresponding to these plurality of pieces of data held by the data hold circuit in a sequence corresponding to the sequence of these plurality of pieces of data.
The first select circuit receives an internal address signal for reading data, and the internal address signal held by the address signal hold circuit which comes first in the sequence, and selectively outputs these internal signals in response to the read/write control signal for reading or writing.
The decode circuit selects a memory cell in the memory cell array in response to the internal address signal output from the first select circuit. The comparison circuit compares the internal address signal for reading out data, and the respective plurality of internal address signals held by the address signal hold circuit in order to output data.
The second select circuit receives the plurality of pieces of data held by the data hold circuit and selectively outputs these pieces of data based on the result of comparison by the comparison circuit, when data is externally read out.
The select output circuit receives the data output from the second select circuit and the data read out by the read/write circuit, and selectively outputs these pieces of data based on the result of comparison by the comparison circuit, when data is externally read out.
Data to be written into the memory cell array is taken in by the data hold circuit when data is not being externally output and a plurality of such data is held in the data hold circuit. Therefore, a conflict of resources does not occur between read data and write data.
A plurality of internal address signals corresponding to the plurality of pieces of data held in the data hold circuit are held by the address hold circuit in a prescribed order, and the hold internal address signals are provided to the decode circuit from the select circuit at the time of writing in response to a read/write control signal, starting from a signal which comes first in the order.
Thus, the period to use the memory cell array for writing the held data can be prolonged through the following period in which the memory cell array is not used which exists at the time of data writing. The prolonged period is determined depending upon the number of address signals and the number of pieces of data held.
Accordingly, a conflict of resources does not occur in the memory cell array. In addition, since the period to take in data does not overlap the period in which the memory cell array is used, a room is provided for timings for taking in data and use of the memory cell array.
Furthermore, if held data is to be read out, one of the held address signals coincides with an internal address for reading data.
Accordingly, if such a coincidence is found-depending upon a comparison result from the comparison circuit, one of the held data may be output from the select output circuit. Accordingly, a request of reading of data which has not yet been written in the memory cell array can be coped with.
As described above, since a conflict of resources can be prevented, delay of a writing operation following a reading operation can be eliminated without increasing chip cost, package cost, and system cost. As a result, high speed operation of cache memories can be achieved and the speed performance of computers of various levels such as supercomputers, large size calculators, work stations and personal computers can be achieved.
In addition, an internal clock generation circuit, a first logic circuit, and a second logic circuit may further be provided, the data hold circuit may include a plurality of first latch circuits, and the address signal hold circuit may include a plurality of second latch circuits.
In such a case, the internal clock generation circuit generates an international clock signal in response to an external clock signal. The first logic circuit generates a first logic signal in response to a delayed read/write control signal and the internal clock signal. The plurality of first latch circuits latch a plurality of pieces of data to be written in memory cells in the memory cell array in the sequence in which they are taken in, in response to the first logic signal.
The second logic circuit generates a second logic signal in response to the internal clock signal and the read/write control signal. The plurality of second latch circuits respond to the second logic signal and latch a plurality of internal address signals corresponding to a plurality of pieces of data to be written in memory cells in said memory cell array, respectively in a sequence corresponding to the sequence of the plurality of pieces of data.
A method of operating a synchronous random access memory according to yet another aspect of the invention is a method of operating a synchronous random access memory having read operations and write operations, each read and write operation executed sequentially,
a read operation comprising a first step of fetching an address, a second step of accessing the random access memory array, and a third step of outputting data, the first through third steps performed in three distinct sequentially machine cycles,
a write operation comprising a first step of fetching an address, a second step of accessing the random access memory array and a third step of inputting data, the first through third steps performed in at least three machine cycles with the second and third steps performed in the same machine cycle or a different machine cycle and the first step performed in a machine cycle which is distinct from the machine cycle in which the second and third steps are performed, the method comprising the step of:
when a write operation is followed by a read operation
in the first machine cycle in which the write operation is, carrying out the first step of write operation,
in the second machine cycle, carrying out the first step of the read operation,
in the third machine cycle, carrying out the third step of the write operation and the second step of the read operation and delaying the second step of the write operation until the second cycle of the next following write operation, and
in the fourth machine cycle, carrying out the third step of the read operation.
If a second write operation follows the write operation, the operation is carried out as follows.
In the first machine cycle, carrying out the first step of the write operation,
in the second machine cycle, carrying out the first step of the second write operation,
in the third machine cycle, carrying out the second and third steps of the write operation, and
in the fourth machine cycle, carrying out the third step of the second write operation, and carrying out the second step of the second write operation when the next operation is a third write operation and delaying the second step of the second write operation until the second cycle of the next following write operation when the next operation is a read operation.
As described above, in carrying out a write operation, the second step of the write operation is carried out in the second machine cycle of the next write operation. The second step of the write operation is thus carried out in the third machine cycle or in the fourth machine cycle or after.
Use of such an operation method can prevent a conflict of resources from being generated. As a result, the operation of the memory can be performed at a high speed.
A method of operating a synchronous random access memory according to a still further aspect of the invention is a method of operating a synchronous random access memory having read operations and write operations, each read and write operation executed sequentially,
a read operation comprising a first step of fetching an address, a second step of accessing the random access memory array, and a third step of outputting data, the first through third steps performed in three distinct sequential machine cycles,
a write operation comprising a first step of fetching an address, a second step of accessing the random access memory array and a third step of inputting data, the first through third steps performed in distinct sequential machine cycles,
the method including the steps of:
when a write operation is carried out,
in the first machine cycle, carrying out the first step of the write operation,
in the second machine cycle, carrying out the first step of a write operation or a read operation following the write operation,
in the third machine cycle, carrying out at least the third step of the write operation and the first step of a write operation or a read operation following after next, and
delaying the second step of the write operation until the second cycle of the third write operation after the fourth machine cycle.
Thus, when a write operation is carried out, the second step of the write operation is carried out in the second cycle of a write operation following the next write operation.
Use of such an operation method can prevent generation of a conflict of resources. As a result, the operation of the memory can be performed at a high speed. Furthermore, since the second and third steps of a write operation are not executed in a single machine cycle, an extra space can be secured for timings for fetching data and using the memory cell array.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.